Network Overlay System and Method Using Offload Processors

ABSTRACT

An input-output (IO) virtualization system connectable to a network is disclosed. The system can include a second virtual switch connected to a memory bus and configured to receive network packets from a first virtual switch, and an offload processor module supporting the second virtual switch, the offload processor module further comprising at least one offload processor configured to modify network packets and direct the modified network packets to the first virtual switch through the memory bus.

PRIORITY CLAIMS

This application claims the benefit of U.S. Provisional PatentApplications 61/753,892 filed on Jan. 17, 2013, 61/753,895 filed on Jan.17, 2013, 61/753,899 filed on Jan. 17, 2013, 61/753,901 filed on Jan.17, 2013, 61/753,903 filed on Jan. 17, 2013, 61/753,904 filed on Jan.17, 2013, 61/753,906 filed on Jan. 17, 2013, 61/753,907 filed on Jan.17, 2013, and 61/753,910 filed on Jan. 17, 2013, the contents all ofwhich are incorporated by reference herein.

TECHNICAL FIELD

Described embodiments relate to input/output (IO) virtualizationservices that are provided by a memory bus connected module that canallow a single IO device to appear as multiple IO devices.

BACKGROUND

Virtualization is commonly seen as a process of combining hardware andsoftware resources into a single administrative entity to simply the useof computing resources. Virtualization can be supported within acomputer or server, across local clusters of computers, or as part of alarger network. Ideally, virtualized systems simplify sharing ofcomputer resources such as storage or processing time. For example,server virtualization can allow an administrator can convert onephysical server into multiple virtual machines. Each virtual server actslike a unique physical device, capable of running its own operatingsystem (OS).

However, support of virtualization can require significant newinvestments in powerful processors, high bandwidth input/output fabrics,and memory upgrades to support increased utilization and computationalrequirements of virtualized systems. Unless additional server classprocessors and high bandwidth interconnects are provided in avirtualized system, a user can experience a significant reduction inaccess time and throughput, diminishing the value of virtualization.

SUMMARY

This disclosure describes embodiments of systems, hardware and methodssuitable for high speed, energy efficient virtualization support thatcan involve minimal or low utilization access to computing resources ofa host processor of a server, server rack system, or blade server. Incertain embodiments, a first virtual switch is connected to the networkand configured to direct network packets based on network identifiertags. A second virtual switch is connected to a memory bus, and anoffload processor module is used to support the second virtual switch.The offload processor module includes at least one offload processorcapable of modifying network packets and directing the modified networkpackets to the first virtual switch through the memory bus.

In other embodiments, the offload processor module includes separatelyaddressable offload processors, and network packets can be directed to aspecific memory address space. The first virtual switch can have directmemory access to the second virtual switch to act as a direct memoryaccess (DMA) master, with the second virtual switch acting as a DMAslave. In other embodiments the master/slave relationship of the virtualswitches can be reversed. The second virtual switch can also have ascheduler and an arbiter to prioritize handling of network data. In thedescribed embodiments, the memory bus supports a data transfer protocol(such as DDR3, as but one very particular example).

In certain embodiments an input-output (IO) virtualization system caninclude a physical IO device and multiple virtual IO devices. Aprovisioning agent is used to allocate exclusive address spaces in amain memory to each of the multiple virtual IO devices and the physicalIO device, with each of the physical or virtual IO devices capable ofdirect memory reads and writes to the respective exclusive addressspaces. The address spaces can be physical or virtual, and theprovisioning agent can create a mapping between virtual addresses andphysical addresses. In selected embodiments, the provisioning agentcreates virtual function (VF) drivers that can optionally be accessiblethrough direct memory address (DMA) and supplied with packet descriptorsto control data processing. Mapping between virtual addresses andphysical addresses can be retained (e.g., stored in tables of an inputoutput memory management unit, IOMMU). A host or server processor can beused to run the provisioning agent. In one embodiment, the secondvirtual switch can be supported by a memory bus attached module havingmultiple offload processors. The memory bus can support a data transferprotocol (such as DDR3, as but one very particular example). Further,the module can be mounted to a memory socket (such as a dual in linememory module (DIMM) socket, as but one particular example).

This disclosure also describes methods for virtualization support byimproved data processing. Received data can be examined at a firstvirtual switch to identify a first target memory address location forthe data. The data is transported to a second virtual switch using amemory bus having a defined memory transport protocol, and the data isthen written to a second target memory location. The data written to thesecond target memory location is processed with an offload processormodule. The offload processor module can include one or more offloadprocessors, and in certain embodiments, multiple low power offloadprocessors having a suitable architecture (such as an ARM typearchitecture, as but one particular example).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1-0 shows a system according to an embodiment.

FIG. 1-1 shows an input output memory management unit (IOMMU) that canbe included in embodiments.

FIG. 1-2 shows a process for providing translation with an IOMMU thatcan be included in embodiments.

FIGS. 1-3 and 1-4 shows a process for assigning packets for processingto various virtual machines, according to an embodiment.

FIGS. 2-0 to 2-3 show processor modules according to variousembodiments.

FIG. 2-4 shows a conventional dual-in-line memory module.

FIG. 2-5 shows a system according to another embodiment.

FIG. 3 shows one particular implementation of a memory bus connectedoffload processor capable of supporting packet conversion services fornetwork overlay that can be included in embodiments.

FIG. 4 shows a process for locking an input output translation lookasidebuffer (IOTLB) that can be included in embodiments.

FIG. 5 shows an example of a virtual switch that can be included inembodiments.

DETAILED DESCRIPTION

Various embodiments of the present invention will now be described indetail with reference to a number of drawings. The embodiments showsystems, devices and methods for providing input/output (IO)virtualization services with minimal impact on a host processor device.The operation of one or more virtual switches can be supported byoffload processor modules that can operate independent of any hostprocessor devices. According to some embodiments, offload processormodules can be connected to a system memory bus and receive data viadirect memory access transfers. In very particular embodiments,processing modules can populate physical slots for connecting in-linememory modules (e.g., DIMMs) to a system memory bus.

FIG. 1-0 is a diagram of a system 100 for providing input/output (IO)virtualization services according to one embodiment. A system 100 caninclude a first virtual switch 106 a, a second virtual switch 106 b, andoffload processors 120. Also shown are a host processor 130, a centralprocessing unit (CPU) input/output (I/O) fabric 114, an input outputmemory management unit (IOMMU) 110, and a memory controller 116. In theparticular embodiment shown, IOMMU 110 can be part of an I/O bridge 107.

In operation, a first virtual switch 106 a can receive data packets 104from, and transmit data packets to a data source 102. A data source 102can include the Internet, a network cloud, inter- or intra-data centernetworks, cluster computers, rack systems, multiple or individualservers, personal computers, or any suitable data packet source ordestination. Data packets can be packet or switch based, although insome embodiments non-packet data is generally converted or encapsulatedinto packets for ease of handling. In some embodiments, data packetshave certain characteristics, including transport protocol number,source and destination port numbers, or source and destination IPaddresses. The data packets can further have associated metadata whichcan help in packet classification and management.

First virtual switch 106 a can include, but is not limited to, devicescompatible with a host bus 108. A virtual switch 106 a can include anetwork interface controller (NIC), a host bus adapter, a convergednetwork adapter, or a switched or ATM network interface, as but a fewexamples. Such controller, interfaces and adapters can include, but arenot limited to, peripheral component interconnect (PCI) and/or PCIexpress (PCIe) devices connecting with host motherboard via PCI or PCIebus (e.g., 108).

A first virtual switch 106 a can employ IO virtualization schemes tomake a single network I/O device appear as multiple devices. Inparticular embodiments this can include a single root I/O virtualization(SR-IOV). SR-IOV permits separate access to resources among various PCIehardware functions by providing both physical control and virtualfunctions. In certain embodiments, the first virtual switch 106 a cansupport OpenFlow or similar software defined networking to abstract outof the control plane. In particular embodiments, the control plane ofthe first virtual switch 106 a can performs functions such as routedetermination, target node identification etc. The forwarding plane ofthe first virtual switch can transport packets from a physical layer ofone kind (Ethernet/IP) to a peripheral IO bus (e.g., 108).

Using IOMMU 110, I/O fabric 114 can interfaces with one or more memorycontrollers 116 to transfer the network packets to a second virtualswitch 106 b. The second virtual switch 106 b, which is interfaced witha memory bus 118, can receive and switch traffic originating from thememory bus 118 to offload processors 120 and vice versa. Thus, theforwarding plane of the second virtual switch 106 b can transportpackets from a memory bus 118 to offload processors 120 or from theoffload processors 120 back onto the memory bus 118. For certainapplications, the described system architecture can allow for relativelydirect communication of network packets to the offload processors 120with minimal or no interruptions to a host processor 130.

Embodiments described herein can include busses of any suitable typesuitable, preferably ones providing high speed low latencyinterconnection between system parts. Bus architectures can include butare not limited to PCI, PCIe, Fibre Channel, and the like. A busarchitecture can also be based on relevant JEDEC standards or include aHyperTransport (HT) architecture. Offload processors 120 can communicateover a memory bus according to any suitable memory bus standard,including but not limited to any of the double data rate (DDR) standards(i.e., DDR, DDR2, DDR3). In some embodiments, offload processors 120 caninclude energy efficient, general purpose processor such as those basedon ARM, ARC, Tensilica, MIPS, Strong/ARM, or RISC architectures. Inaddition to processors, offload processors 120 can include, or operatein conjunction with, memory devices. Such memory devices can include butnot limited to DDR dynamic random access memory (RAM), reduced latencyDRAM (RLDRAM), or next generation stacked memory devices, such as HybridMemory Cube (HMC), flash, or other suitable memory. Offload processors120 can also include embedded memory (e.g., embedded DRAM), separatelogic or bus management chips, programmable units such as fieldprogrammable gate arrays (FPGAs), custom designed application specificintegrated circuits (ASICs).

In some embodiments, a host processor 130 can be a general purposeprocessor, including those based on Intel or AMD x86 architecture, IntelItanium architecture, MIPS architecture, SPARC architecture or the like.

Referring still to FIG. 1-0, an operating system, or the user coderunning on the host processor 130, may be loaded with a device model135, one or more virtual function (VF) drivers 132 and controllingfunction (CF) drivers 133 using a provisioning agent 130 a. Theprovisioning agent 130 a can be an entity on the host processor 130 thatcan initializes and interact with virtual VF drivers 132. The VF driver132 can be responsible for providing a VF with the virtual address ofthe memory space where direct memory addressing (DMA) is needed. Each VFdriver can be allocated with virtual addresses that can map to physicaladdresses. A device model 135 can be used to create an emulation of aphysical device for the host processor 130 to recognize each of themultiple VFs that are created. The device model 135 can be replicatedmultiple times to give the impression to VF drivers (a driver thatinteracts with a virtual IO device) that they are interacting with aphysical device. For example, a device model to emulate a networkadapter can be the Intel® Ethernet Converged Network Adapter (CNA)X540-T2. The VF driver 132 can act to connect with such an adapter. Thedevice model 135 and the VF driver 133 can be run in either privilegedor non-privileged mode. There can be no restriction with regard to whichdevice hosts/runs the code corresponding to the device model and the VFdriver. The code, however, can have the capability to create multiplecopies of device model and VF driver so as to enable multiple copies ofsaid I/O interface to be created.

An operating system of a host processor 130 can also create a definedphysical address space for an application 130 a supporting the VFdrivers 132. Further, the host processor 130 operating system canallocate a virtual memory address space to the application orprovisioning agent 130 a. The provisioning agent 130 a can broker withthe host operating system to create a mapping between said virtualaddress and a subset of the available physical address space. Thisphysical address space corresponds to the address space of the offloadprocessors 120. The provisioning agent 130 a can be responsible forcreating each VF driver 132 and allocating to it a defined virtualaddress space. The application or provisioning agent 130 a can controlthe operation of each of the VF drivers. The provisioning agent 130 acan supply each VF driver 132 with descriptors such as an address of anext packet.

An application or provisioning agent 130 a, as part of anapplication/user level code, can create a virtual address space for eachVF 132 during runtime. Allocating an address space to a device can besupported by allocating to the virtual address space a portion of theavailable physical memory space. This allocates part of the physicaladdress space to the VF. For example, if the application 130 a handlingthe VF driver 132 instructs it to read or write packets from or tovirtual memory addresses 0xaaaa to 0xffff, the VF driver may write I/Odescriptors into a descriptor queue of a VF with a head and tail pointerthat are changed dynamically as queue entries are filled. The datastructure may be of another type as well, including but not limited to aring structure or hash table.

A mapping between virtual memory address space and physical memory spacecan be stored in tables of an IOMMU 110. An application may supply VFdrivers 132 with virtual addresses at which memory read or write is tobe performed. The VF drivers 132 supply the virtual addresses to a VF.The VFs are configured to generate requests such as read and write whichmay be part of a direct memory access (DMA) read or write operation. AVF can read from or write data to the address location pointed to by theVF driver. The virtual addresses are translated by the IOMMU 110 tocorresponding physical addresses and the physical addresses may beprovided to the memory controller for access. That is, the IOMMU 110 canmodify the memory requests sourced by the I/O devices to change thevirtual address in the request to a physical address. The memory requestcan then be forwarded to the memory controller 116 for memory access.Further, on completing the transfer of data to the address spaceallocated to the VF driver 132, the VF driver can mask or disable thoseinterrupts, which are usually forwarded to the host processor 130 tohandle such data (e.g., network packets). The memory request may beforwarded to memory controller 116 over a high speed low latencyinterconnection 112 (e.g., HyperTransport, HT) 112. The VF in such casescan carry out a direct memory access by supplying the virtual memoryaddress to the IOMMU 110.

Alternatively, an application may directly code the physical addressinto the VF descriptors if the VF allows for it. If the VF cannotsupport physical addresses of the form used by the host processor 130,an aperture with a hardware size supported by the VF device may be codedinto the descriptor so that the VF is informed of the target hardwareaddress of the device. Data that is transferred to an aperture may bemapped by a translation table to a defined physical address space in thesystem memory. DMA operations may be initiated by software executed bythe processors, programming the I/O devices directly or indirectly toperform the DMA operations.

FIG. 1-1 shows an IOMMU 110′ that can be included in embodiments. AnIOMMU 110′ can be configured to translate a virtual address (DEVICEVISIBLE VIRTUAL ADDRESS) corresponding to an I/O device to itscorresponding physical address in the main memory (PHYSICAL ADDRESS).The IOMMU 110′ may include page table walker 110 a, a translationlookaside buffer (IOTLB) 110 b, control registers 110 c, and controllogic 110 d.

FIG. 1-2 is a flow diagram showing an IOMMU method 150 to serve I/Orequests that can be included in the embodiments. A method 150 caninclude receiving an I/O request (for address translation) (151). If theaddress translation is already available in the IOTLB 110 b (Yes from152), the information can be sent to a memory controller (152) (thusserving the request). Otherwise (No from 152), a page table walker canbe invoked (153), and a translated address can be obtained and providedto the memory controller. An IOTLB of the IOMMU can be updated with thislatest translation information (154) and an event log can be created orupdated (155).

FIGS. 1-3 and 1-4 together illustrate a process flow 160 according to anembodiment. Referring to FIG. 1-3, a process 160 can include receivingpackets from a network (162). Packets can be segregated based onsessions (164). Such an action can include classifying packets based onsession metadata with a virtualized network interface. In the embodimentshown, this can include operation of a first virtual switch (e.g., 106 aof FIG. 1-0). Sessions can be prioritized and queued for arbitration(166). Using session metadata, a determination can be made if sessionsare to be written to offload processors (168). Such an action can useboth packet metadata and session metadata. If session(s) are not to bewritten to offload processors (No from 168), session(s) can be queuedfor a host processor(s) (170). If sessions are for offload processors(Yes from 168), based on a classification, packet(s) can be assigned toone of multiple VFs (172). VFs can be supplied with virtual memoryaddresses by a VF driver. The VFs can use the virtual memory addressesto generate a DMA request. The request can be forwarded to an IOMMU(174). Such actions can use other details in a descriptor structure togenerate the DMA request.

Referring to FIG. 1-4, a process 160 can further include the IOMMUperforming an address translation to identify a physical addresscorresponding to a supplied virtual address (176). The IOMMU can forwardthe DMA request to a memory controller (178). The DMA request can betargeted to the physical address generated at 176. Therefore, thepackets destined to be processed by the offload processors can bewritten to the memory location corresponding to the offload processorsby performing a DMA operation. Data (e.g., packets) written to a memorylocation by memory controller can be received by a second virtual switch(180). The second virtual switch can carry out traffic management toreintroduce prioritization based on metadata (182). Such actions caninclude classification and prioritization to create flow characteristicsfor packets of a session using available session metadata. Arbitrationbetween different sessions can occur, and different sessions can bescheduled into different offload processors (184). Such action canresult in traffic managed flows being written to multiple offloadprocessors at, with execution of data processing operations determinedby suitable arbiters and schedulers. In particular embodiments, suchaction can include offload processors operating on the packet data,where the offload processors are mounted to a memory bus subject to theDMA transfer. In one very particular embodiment, such offload processormodules can be fitted into a memory bus socket, such as a DIMM slot.

It is understood that many of the foregoing processing tasks can beimplemented on multiple threads running on multiple processing cores.Such parallelization of tasks into multiple thread contexts can providefor increased throughput. Processors architectures such as MIPS mayinclude deep instruction pipelines to improve the number of instructionsper cycle. Further, the ability to run a multi-threaded programmingenvironment results in enhanced usage of existing processor resources.To further increase parallel execution on the hardware, processorarchitecture may include multiple processor cores. Multi-corearchitectures comprising the same type of cores, referred to ashomogeneous core architectures, provide higher instruction throughput byparallelizing threads or processes across multiple cores. However, insuch homogeneous core architectures, the shared resources, such asmemory, are amortized over a small number of processors. In still otherembodiments, multiple offload or host processors can reside on modulesconnected to individual rack units or blades that in turn reside onracks or individual servers. These can be further grouped into clustersand datacenters, which can be spatially located in the same building, inthe same city, or even in different countries. Any grouping level can beconnected to each other, and/or connected to public or private cloudinternets.

Memory and I/O accesses can incur a high amount of processor overhead.Further, context switches in conventional general purpose processingunits can be computationally intensive. It is therefore desirable toreduce context switch overhead in a networked computing resourcehandling a plurality of networked applications in order to increaseprocessor throughput. Conventional server loads can require complextransport, high memory bandwidth, extreme amounts of data bandwidth(randomly accessed, parallelized, and highly available), but often withlight touch processing: HTML, video, packet-level services, security,and analytics. Further, idle processors still consume more than 50% oftheir peak power consumption.

In contrast, according to embodiments herein, complex transport, databandwidth intensive, frequent random access oriented, ‘light’ touchprocessing loads can be handled behind a socket abstraction created onmultiple offload processor cores. At the same time, “heavy” touch,computing intensive loads can be handled by a socket abstraction on ahost processor core (e.g., x86 processor cores). Such software socketscan allow for a natural partitioning of these loads between light touch(e.g., ARM) and heavy touch (e.g., x86) processor cores. By usage of newapplication level sockets, according to embodiments, server loads can bebroken up across the offload processing cores and the host processingcores.

FIGS. 2-0 to 2-5 describe aspects of hardware embodiments and methodsuseful for providing IO virtualization services using an offloadprocessor module to support offload processing as described herein, orequivalents. In particular embodiments, such processing modules caninclude DIMM mountable modules.

FIG. 2-0 is a block diagram of a processing module 200 according to oneembodiment. A processing module 200 can include a physical connector202, a memory interface 204, arbiter logic 206, offload processor(s)208, local memory 210, and control logic 212. A connector 202 canprovide a physical connection to system memory bus. This is in contrastto a host processor which can access a system memory bus via a memorycontroller, or the like. In very particular embodiments, a connector 202can be compatible with a dual in-line memory module (DIMM) slot of acomputing system. Accordingly, a system including multiple DIMM slotscan be populated with one or more processing modules 200, or a mix ofprocessing modules and DIMM modules.

A memory interface 204 can detect data transfers on a system memory bus,and in appropriate cases, enable write data to be stored in theprocessing module 200 and/or read data to be read out from theprocessing module 200. Such data transfers can include the receipt ofpacket data having a particular network identifier. In some embodiments,a memory interface 204 can be a slave interface, thus data transfers arecontrolled by a master device separate from the processing module 200.In very particular embodiments, a memory interface 204 can be a directmemory access (DMA) slave, to accommodate DMA transfers over a systemmemory bus initiated by a DMA master. In some embodiments, a DMA mastercan be a device different from a host processor. In such configurations,processing module 200 can receive data for processing (e.g., DMA write),and transfer processed data out (e.g., DMA read) without consuming hostprocessor resources.

Arbiter logic 206 can arbitrate between conflicting accesses of datawithin processing module 200. In some embodiments, arbiter logic 206 canarbitrate between accesses by offload processor 208 and accessesexternal to the processor module 200. It is understood that a processingmodule 200 can include multiple locations that are operated on at thesame time. It is understood that accesses arbitrated by arbiter logic206 can include accesses to physical system memory space occupied by theprocessor module 200, as well as accesses to other resources (e.g.,cache memory of offload or host processor). Accordingly, arbitrationrules for arbiter logic 206 can vary according to application. In someembodiments, such arbitration rules are fixed for a given processormodule 200. In such cases, different applications can be accommodated byswitching out different processing modules. However, in alternateembodiments, such arbitration rules can be configurable.

Offload processor 208 can include one or more processors that canoperate on data transferred over the system memory bus. In someembodiments, offload processors can run a general operating system orserver applications such as Apache (as but one very particular example),enabling processor contexts to be saved and retrieved. Computing tasksexecuted by offload processor 208 can be handled by the hardwarescheduler. Offload processors 208 can operate on data buffered in theprocessor module 200. In addition or alternatively, offload processors208 can access data stored elsewhere in a system memory space. In someembodiments, offload processors 208 can include a cache memoryconfigured to store context information. An offload processor 208 caninclude multiple cores or one core.

A processor module 200 can be included in a system having a hostprocessor (not shown). In some embodiments, offload processors 208 canbe a different type of processor as compared to the host processor. Inparticular embodiments, offload processors 208 can consume less powerand/or have less computing power than a host processor. In veryparticular embodiments, offload processors 208 can be “wimpy” coreprocessors, while a host processor can be a “brawny” core processor.However, in alternate embodiments, offload processors 208 can haveequivalent computing power to any host processor. In very particularembodiments, a host processor can be an x86 type processor, while anoffload processor 208 can include an ARM, ARC, Tensilica, MIPS,Strong/ARM, or RISC type processor, as but a few examples. Local memory210 can be connected to offload processor 208 to enable the storing ofcontext information. Accordingly, an offload processor 208 can storecurrent context information, and then switch to a new computing task,then subsequently retrieve the context information to resume the priortask. In very particular embodiments, local memory 210 can be a lowlatency memory with respect to other memories in a system. In someembodiments, storing of context information can include copying anoffload processor 208 cache.

In some embodiments, a same space within local memory 210 is accessibleby multiple offload processors 208 of the same type. In this way, acontext stored by one offload processor can be resumed by a differentoffload processor.

Control logic 212 can control processing tasks executed by offloadprocessor(s). In some embodiments, control logic 212 can be considered ahardware scheduler that can be conceptualized as including a dataevaluator 214, scheduler 216 and a switch controller 218. A dataevaluator 214 can extract “metadata” from write data transferred over asystem memory bus. “Metadata”, as used herein, can be any informationembedded at one or more predetermined locations of a block of write datathat indicates processing to be performed on all or a portion of theblock of write data and/or indicate a particular task/process to whichthe data belongs (e.g., classification data). In some embodiments,metadata can be data that indicates a higher level organization for theblock of write data. As but one very particular embodiment, metadata canbe header information of one or more network packets (which may or maynot be encapsulated within a higher layer packet structure).

A scheduler 216 (e.g., a hardware scheduler) can order computing tasksfor offload processor(s) 208. In some embodiments, scheduler 216 cangenerate a schedule that is continually updated as write data forprocessing is received. In very particular embodiments, a scheduler 216can generate such a schedule based on the ability to switch contexts ofoffload processor(s) 208. In this way, on-module computing prioritiescan be adjusted on the fly. In very particular embodiments, a scheduler216 can assign a portion of physical address space (e.g., memorylocations within local memory 210) to an offload processor 208,according to computing tasks. The offload processor 208 can then switchbetween such different spaces, saving context information prior to eachswitch, and subsequently restoring context information when returning tothe memory space.

Switch controller 218 can control computing operations of offloadprocessor(s) 208. In particular embodiments, according to scheduler 216,switch controller 218 can order offload processor(s) 208 to switchcontexts. It is understood that a context switch operation can be an“atomic” operation, executed in response to a single command from switchcontroller 218. In addition or alternatively, a switch controller 218can issue an instruction set that stores current context information,recalls context information, etc.

In some embodiments, processor module 200 can include a buffer memory(not shown). A buffer memory can store received write data on board theprocessor module. A buffer memory can be implemented on an entirelydifferent set of memory devices, or can be a memory embedded with logicand/or the offload processor. In the latter case, arbiter logic 206 canarbitrate access to the buffer memory. In some embodiments, a buffermemory can correspond to a portion of a system physical memory space.The remaining portion of the system memory space can correspond to otherlike processor modules and/or memory modules connected to the samesystem memory bus. In some embodiments buffer memory can be differentthan local memory 210. For example, buffer memory can have a sloweraccess time than local memory 210. However, in other embodiments, buffermemory and local memory can be implemented with like memory devices.

In very particular embodiments, write data for processing can have anexpected maximum flow rate. A processor module 200 can be configured tooperate on such data at, or faster than, such a flow rate. In this way,a master device (not shown) can write data to a processor module withoutdanger of overwriting data “in process”.

The various computing elements of a processor module 200 can beimplemented as one or more integrated circuit devices (ICs). It isunderstood that the various components shown in FIG. 2-0 can be formedin the same or different ICs. For example, control logic 212, memoryinterface 214, and/or arbiter logic 206 can be implemented on one ormore logic ICs, while offload processor(s) 208 and local memory 210 areseparate ICs. Logic ICs can be fixed logic (e.g., application specificICs), programmable logic (e.g., field programmable gate arrays, FPGAs),or combinations thereof.

Advantageously, the foregoing hardware and systems can provide improvedcomputational performance as compared to traditional computing systems.Conventional systems, including those based on x86 processors, are oftenill-equipped to handle such high volume applications. Even idling, x86processors use a significant amount of power, and near continuousoperation for high bandwidth packet analysis or other high volumeprocessing tasks makes the processor energy costs one of the dominantprice factors.

In addition, conventional systems can have issues with the high cost ofcontext switching wherein a host processor is required to executeinstructions which can include switching from one thread to another.Such a switch can require storing and recalling the context for thethread. If such context data is resident in a host cache memory, such acontext switch can occur relatively quickly. However, if such contextdata is no longer in cache memory (i.e., a cache miss), the data must berecalled from system memory, which can incur a multi-cycle latency.Continuous cache misses during context switching can adversely impactsystem performance.

FIG. 2-1 shows a processor module 200-1 according to one very particularembodiment which is capable of reducing issues associated with highvolume processing or context switching associated with many conventionalserver systems. A processor module 200-1 can include ICs 220-0/1 mountedto a printed circuit board (PCB) type substrate 222. PCB type substrate222 can include in-line module connector 202, which in one veryparticular embodiment, can be a DIMM compatible connector. IC 220-0 canbe a system-on-chip (SoC) type device, integrating multiple functions.In the very particular embodiment shown, an IC 220-0 can includeembedded processor(s), logic and memory. Such embedded processor(s) canbe offload processor(s) 208 as described herein, or equivalents. Suchlogic can be any of controller logic 212, memory interface 204 and/orarbiter logic 206, as described herein, or equivalents. Such memory canbe any of local memory 210, cache memory for offload processor(s) 208,or buffer memory, as described herein, or equivalents. Logic IC 220-1can provide logic functions not included IC 220-0.

FIG. 2-2 shows a processor module 200-2 according to another veryparticular embodiment. A processor module 200-2 can include ICs 220-2,-3, -4, -5 mounted to a PCB type substrate 222, like that of FIG. 2-1.However, unlike FIG. 2-1, processor module functions are distributedamong single purpose type ICs. IC 220-2 can be a processor IC, which canbe an offload processor 208. IC 220-3 can be a memory IC which caninclude local memory 210, buffer memory, or combinations thereof. IC220-4 can be a logic IC which can include control logic 212, and in onevery particular embodiment, can be an FPGA. IC 220-5 can be anotherlogic IC which can include memory interface 204 and arbiter logic 206,and in one very particular embodiment, can also be an FPGA.

It is understood that FIGS. 2-1/2 represent but two of variousimplementations. The various functions of a processor module can bedistributed over any suitable number of ICs, including a single SoC typeIC.

FIG. 2-3 shows an opposing side of a processor module 200-1 or 200-2according to a very particular embodiment. Processor module 200-3 caninclude a number of memory ICs, one shown as 220-6, mounted to a PCBtype substrate 222, like that of FIG. 2-1. It is understood that variousprocessing and logic components can be mounted on an opposing side tothat shown. A memory IC 220-6 can be configured to represent a portionof the physical memory space of a system. Memory ICs 220-6 can performany or all of the following functions: operate independently of otherprocessor module components, providing system memory accessed in aconventional fashion; serve as buffer memory, storing write data thatcan be processed with other processor module components, or serve aslocal memory for storing processor context information.

FIG. 2-4 shows a conventional DIMM module (i.e., it serves only a memoryfunction) that can populate a memory bus along with processor modules asdescribed herein, or equivalents.

FIG. 2-5 shows a system 230 according to one embodiment. A system 230can include a system memory bus 228 accessible via multiple in-linemodule slots (one shown as 226). According to embodiments, any or all ofthe slots 226 can be occupied by a processor module 200 as describedherein, or an equivalent. In the event all slots 226 are not occupied bya processor module 200, available slots can be occupied by conventionalin-line memory modules 224. In a very particular embodiment, slots 226can be DIMM slots.

In some embodiments, a processor module 200 can occupy one slot.However, in other embodiments, a processor module can occupy multipleslots.

In some embodiments, a system memory bus 228 can be further interfacedwith one or more host processors and/or input/output device (not shown).

Having described processor modules according to various embodiments,operations of an offload processor module capable of interfacing withserver or similar system via a memory bus and according to a particularembodiment will now be described.

FIG. 3 shows a system 301 that can receive and process packet datadirected to it by IO virtualization, as described herein or equivalents.A system 301 can transport packet data requiring network overlayservices to one or more computational units (one shown as 300) locatedon a module, which in particular embodiments, can include a connectorcompatible with an existing memory module. In some embodiments, acomputational unit 300 can include a processor module as described inembodiments herein, or an equivalent. A computational unit 300 can becapable of intercepting or otherwise accessing packets sent over amemory bus 316 and carrying out processing on such packets, includingbut not limited to termination or metadata processing. A system memorybus 316 can be a system memory bus like those described herein, orequivalents (e.g., 228).

Referring still to FIG. 3, a system 301 can include an I/O device 302which can receive packet or other I/O data from an external source. Insome embodiments I/O device 302 can include physical or virtualfunctions generated by the physical device to receive a packet or otherI/O data from the network or another computer or virtual machine. In thevery particular embodiment shown, an I/O device 302 can include anetwork interface card (NIC) having input buffer 302 a (e.g., DMA ringbuffer) and an I/O virtualization function 302 b.

According to embodiments, an I/O device 302 can write a descriptorincluding details of the necessary memory operation for the packet (i.e.read/write, source/destination). Such a descriptor can be assigned avirtual memory location (e.g., by an operating system of the system301). I/O device 302 then communicates with an input output memorymanagement unit (IOMMU) 304 which can translate virtual addresses tocorresponding physical addresses with an IOMMU function 304 b. In theparticular embodiment shown, a translation look-aside buffer (TLB) 304 acan be used for such translation. Virtual function reads or writes databetween I/O device and system memory locations can then be executed witha direct memory transfer (e.g., DMA) via a memory controller 306 b ofthe system 301. An I/O device 302 can be connected to IOMMU 304 by ahost bus 312. In one very particular embodiment, a host bus 312 can be aperipheral interconnect (PCI) type bus. IOMMU 304 can be connected to ahost processing section 306 at a central processing unit I/O (CPUIO) 306a. In the embodiment shown, such a connection 314 can support aHyperTransport (HT) protocol.

In the embodiment shown, a host processing section 306 can include theCPUIO 306 a, memory controller 306 b, processing core 306 c andcorresponding provisioning agent 306 d.

In particular embodiments, a computational unit 300 can interface withthe system bus 316 via standard in-line module connection, which in veryparticular embodiments can include a DIMM type slot. In the embodimentshown, a memory bus 316 can be a DDR3 type memory bus. Alternateembodiments can include any suitable system memory bus. Packet data canbe sent by memory controller 306 b via memory bus 316 to a DMA slaveinterface 310 a. DMA slave interface 310 a can be adapted to receiveencapsulated read/write instructions from a DMA write over the memorybus 316.

A hardware scheduler (308 b/c/d/e/h) can perform traffic management onincoming packets by categorizing them according to flow using sessionmetadata. Packets can be queued for output in an onboard memory (310b/308 a/308 m) based on session priority. When the hardware schedulerdetermines that a packet for a particular session is ready to beprocessed by the offload processor 308 i, the onboard memory is signaledfor a context switch to that session. Utilizing this method ofprioritization, context switching overhead can be reduced, as comparedto conventional approaches. That is, a hardware scheduler can handlecontext switching decisions and thus optimize the performance of thedownstream resource (e.g., offload processor 308 i).

As noted above, in very particular embodiments, an offload processor 308i can be a “wimpy core” type processor. According to some embodiments, ahost processor 306 c can be a “brawny core” type processor (e.g., an x86or any other processor capable of handling “heavy touch” computationaloperations). While an I/O device 302 can be configured to trigger hostprocessor interrupts in response to incoming packets, according toembodiments, such interrupts can be disabled, thereby reducingprocessing overhead for the host processor 306 c. In some veryparticular embodiments, an offload processor 308 i can include an ARM,ARC, Tensilica, MIPS, Strong/ARM or any other processor capable ofhandling “light touch” operations. Preferably, an offload processor canrun a general purpose operating system for executing a plurality ofsessions, which can be optimized to work in conjunction with thehardware scheduler in order to reduce context switching overhead.

Referring still to FIG. 3, in operation, a system 301 can receivepackets from an external network over a network interface. The packetsare destined for either a host processor 306 c or an offload processor308 i based on the classification logic and schematics employed by I/Odevice 302. In particular embodiments, I/O device 302 can operate as avirtualized NIC, with packets for a particular logical network or to acertain virtual MAC (VMAC) address can be directed into separate queuesand sent over to the destination logical entity. Such an arrangement cantransfer packets to different entities. In some embodiments, each suchentity can have a virtual driver, a virtual device model that it uses tocommunicate with connected virtual network.

According to embodiments, multiple devices can be used to redirecttraffic to specific memory addresses. So, each of the network devicesoperates as if it is transferring the packets to the memory location ofa logical entity. However, in reality, such packets are transferred tomemory addresses where they can be handled by one or more offloadprocessors (e.g., 308 i). In particular embodiments such transfers areto physical memory addresses, thus logical entities can be removed fromthe processing, and a host processor can be free from such packethandling.

Accordingly, embodiments can be conceptualized as providing a memory“black box” to which specific network data can be fed. Such a memoryblack box can handle the data (e.g., process it) and respond back whensuch data is requested.

Referring still to FIG. 3, according to some embodiments, I/O device 302can receive data packets from a network or from a computing device. Thedata packets can have certain characteristics, including transportprotocol number, source and destination port numbers, source anddestination IP addresses, for example. The data packets can further havemetadata that is processed (308 d) that helps in their classificationand management.

I/O device 302 can include, but is not limited to, peripheral componentinterconnect (PCI) and/or PCI express (PCIe) devices connecting with ahost motherboard via PCI or PCIe bus (e.g., 312). Examples of I/Odevices include a network interface controller (NIC), a host busadapter, a converged network adapter, an ATM network interface, etc.

In order to provide for an abstraction scheme that allows multiplelogical entities to access the same I/O device 302, the I/O device maybe virtualized to provide for multiple virtual devices each of which canperform some of the functions of the physical I/O device. The IOvirtualization program (e.g., 302 b) according to an embodiment, canredirect traffic to different memory locations (and thus to differentoffload processors attached to modules on a memory bus). To achievethis, an I/O device 302 (e.g., a network card) may be partitioned intoseveral function parts; including controlling function (CF) supportinginput/output virtualization (IOV) architecture (e.g., single-root IOV)and multiple virtual function (VF) interfaces. Each virtual functioninterface may be provided with resources during runtime for dedicatedusage. Examples of the CF and VF may include the physical function andvirtual functions under schemes such as Single Root I/O Virtualizationor Multi-Root I/O Virtualization architecture. The CF acts as thephysical resources that sets up and manages virtual resources. The CF isalso capable of acting as a full-fledged IO device. The VF isresponsible for providing an abstraction of a virtual device forcommunication with multiple logical entities/multiple memory regions.

The operating system/the hypervisor/any of the virtual machines/usercode running on a host processor 306 c may be loaded with a devicemodel, a VF driver and a driver for a CF. The device model may be usedto create an emulation of a physical device for the host processor 306 cto recognize each of the multiple VFs that are created. The device modelmay be replicated multiple times to give the impression to a VF driver(a driver that interacts with a virtual IO device) that it isinteracting with a physical device of a particular type.

For example, a certain device module may be used to emulate a networkadapter such as the Intel® Ethernet Converged Network Adapter(CNA)X540-T2, so that the I/O device 302 believes it is interacting with suchan adapter. In such a case, each of the virtual functions may have thecapability to support the functions of the above said CNA, i.e., each ofthe Physical Functions should be able to support such functionality. Thedevice model and the VF driver can be run in either privileged ornon-privileged mode. In some embodiments, there is no restriction withregard to who hosts/runs the code corresponding to the device model andthe VF driver. The code, however, has the capability to create multiplecopies of device model and VF driver so as to enable multiple copies ofsaid I/O interface to be created.

An application or provisioning agent 306 d, as part of anapplication/user level code running in a kernel, may create a virtualI/O address space for each VF, during runtime and allocate part of thephysical address space to it. For example, if an application handlingthe VF driver instructs it to read or write packets from or to memoryaddresses 0xaaaa to 0xffff, the device driver may write I/O descriptorsinto a descriptor queue with a head and tail pointer that are changeddynamically as queue entries are filled. The data structure may be ofanother type as well, including but not limited to a ring structure 302a or hash table.

The VF can read from or write data to the address location pointed to bythe driver. Further, on completing the transfer of data to the addressspace allocated to the driver, interrupts, which are usually triggeredto the host processor to handle said network packets, can be disabled.Allocating a specific I/O space to a device can include allocating saidIO space a specific physical memory space occupied.

In another embodiment, the descriptor may comprise only a writeoperation, if the descriptor is associated with a specific datastructure for handling incoming packets. Further, the descriptor foreach of the entries in the incoming data structure may be constant so asto redirect all data write to a specific memory location. In analternate embodiment, the descriptor for consecutive entries may pointto consecutive entries in memory so as to direct incoming packets toconsecutive memory locations.

Alternatively, said operating system may create a defined physicaladdress space for an application supporting the VF drivers and allocatea virtual memory address space to the application or provisioning agent306 d, thereby creating a mapping for each virtual function between saidvirtual address and a physical address space. Said mapping betweenvirtual memory address space and physical memory space may be stored inIOMMU tables (e.g., a TLB 304 a). The application performing memoryreads or writes may supply virtual addresses to say virtual function,and the host processor OS may allocate a specific part of the physicalmemory location to such an application.

Alternatively, VF may be configured to generate requests such as readand write which may be part of a direct memory access (DMA) read orwrite operation, for example. The virtual addresses is be translated bythe IOMMU 304 to their corresponding physical addresses and the physicaladdresses may be provided to the memory controller for access. That is,the IOMMU 304 may modify the memory requests sourced by the I/O devicesto change the virtual address in the request to a physical address, andthe memory request may be forwarded to the memory controller for memoryaccess. The memory request may be forwarded over a bus 314 that supportsa protocol such as HyperTransport 314. The VF may in such cases carryout a direct memory access by supplying the virtual memory address tothe IOMMU 304.

Alternatively, said application may directly code the physical addressinto the VF descriptors if the VF allows for it. If the VF cannotsupport physical addresses of the form used by the host processor 306 c,an aperture with a hardware size supported by the VF device may be codedinto the descriptor so that the VF is informed of the target hardwareaddress of the device. Data that is transferred to an aperture may bemapped by a translation table to a defined physical address space in thesystem memory. The DMA operations may be initiated by software executedby the processors, programming the I/O devices directly or indirectly toperform the DMA operations.

Referring still to FIG. 3, in particular embodiments, parts ofcomputational unit 300 can be implemented with one or more FPGAs. In thesystem of FIG. 3, computational unit 300 can include FPGA 310 in whichcan be formed a DMA slave device module 310 a and arbiter 310 f. A DMAslave module 310 a can be any device suitable for attachment to a memorybus 316 that can respond to DMA read/write requests. In alternateembodiments, a DMA slave module 310 a can be another interface capableof block data transfers over memory bus 316. The DMA slave module 310 acan be capable of receiving data from a DMA controller (when it performsa read from a ‘memory’ or from a peripheral) or transferring data to aDMA controller (when it performs a write instruction on the DMA slavemodule 310 a). The DMA slave module 310 a may be adapted to receive DMAread and write instructions encapsulated over a memory bus, (e.g., inthe form of a DDR data transmission, such as a packet or data burst), orany other format that can be sent over the corresponding memory bus.

A DMA slave module 310 a can reconstruct the DMA read/write instructionfrom the memory R/W packet. The DMA slave module 310 a may be adapted torespond to these instructions in the form of data reads/data writes tothe DMA master, which could either be housed in a peripheral device, inthe case of a PCIe bus, or a system DMA controller in the case of an ISAbus.

I/O data that is received by the DMA device 310 a can then queued forarbitration. Arbitration can include the process of scheduling packetsof different flows, such that they are provided access to availablebandwidth based on a number of parameters. In general, an arbiter 310 fprovides resource access to one or more requestors. If multiplerequestors request access, an arbiter 310 f can determine whichrequestor becomes the accessor and then passes data from the accessor tothe resource interface, and the downstream resource can begin executionon the data. After the data has been completely transferred to aresource, and the resource has competed execution, the arbiter 310 f cantransfer control to a different requestor and this cycle repeats for allavailable requestors. In the embodiment of FIG. 3 arbiter 310 f cannotify other portions of computational unit 300 (e.g., 308) of incomingdata.

Alternatively, a computation unit 300 can utilize an arbitration schemeshown in U.S. Pat. No. 7,813,283, issued to Dalal on Oct. 12, 2010, thecontents of which are incorporated herein by reference. Other suitablearbitration schemes known in art could be implemented in embodimentsherein. Alternatively, the arbitration scheme of the current inventionmight be implemented using an OpenFlow switch and an OpenFlowcontroller.

In the very particular embodiment of FIG. 3, computational unit 300 canfurther include notify/prefetch circuits 310 c which can prefetch datastored in a buffer memory 310 b in response to DMA slave module 310 a,and as arbitrated by arbiter 310 f. Further, arbiter 310 f can accessother portions of the computational unit 300 via a memory mapped I/Oingress path 310 e and egress path 310 g.

Referring to FIG. 3, a hardware scheduler can include a schedulingcircuit 308 b/n to implement traffic management of incoming packets.Packets from a certain source, relating to a certain traffic class,pertaining to a specific application or flowing to a certain socket arereferred to as part of a session flow and are classified using sessionmetadata. Such classification can be performed by classifier 308 e.

In some embodiments, session metadata 308 d can serve as the criterionby which packets are prioritized and scheduled and as such, incomingpackets can be reordered based on their session metadata. Thisreordering of packets can occur in one or more buffers and can modifythe traffic shape of these flows. The scheduling discipline chosen forthis prioritization, or traffic management (TM), can affect the trafficshape of flows and micro-flows through delay (buffering), bursting oftraffic (buffering and bursting), smoothing of traffic (buffering andrate-limiting flows), dropping traffic (choosing data to discard so asto avoid exhausting the buffer), delay jitter (temporally shifting cellsof a flow by different amounts) and by not admitting a connection (e.g.,cannot simultaneously guarantee existing service level agreements (SLAB)with an additional flow's SLA).

According to embodiments, computational unit 300 can serve as part of aswitch fabric, and provide traffic management with depth-limited outputqueues, the access to which is arbitrated by a scheduling circuit 308b/n. Such output queues are managed using a scheduling discipline toprovide traffic management for incoming flows. The session flows queuedin each of these queues can be sent out through an output port to adownstream network element.

It is noted that conventional traffic management do not take intoaccount the handling and management of data by downstream elementsexcept for meeting the SLA agreements it already has with saiddownstream elements.

In contrast, according to embodiments a scheduler circuit 308 b/n canallocate a priority to each of the output queues and carry outreordering of incoming packets to maintain persistence of session flowsin these queues. A scheduler circuit 308 b/n can be used to control thescheduling of each of these persistent sessions into a general purposeoperating system (OS) 308 j, executed on an offload processor 308 i.Packets of a particular session flow, as defined above, can belong to aparticular queue. The scheduler circuit 308 b/n may control theprioritization of these queues such that they are arbitrated forhandling by a general purpose (GP) processing resource (e.g., offloadprocessor 308 i) located downstream. An OS 308 j running on a downstreamprocessor 308 i can allocate execution resources such as processorcycles and memory to a particular queue it is currently handling. The OS308 j may further allocate a thread or a group of threads for thatparticular queue, so that it is handled distinctly by the generalpurpose processing element 308 i as a separate entity. The fact thatthere can be multiple sessions running on a GP processing resource, eachhandling data from a particular session flow resident in a queueestablished by the scheduler circuit, tightly integrates the schedulerand the downstream resource (e.g., 308 i). This can bring aboutpersistence of session information across the traffic management andscheduling circuit and the general purpose processing resource 308 i.

Dedicated computing resources (e.g., 308 i), memory space and sessioncontext information for each of the sessions can provide a way ofhandling, processing and/or terminating each of the session flows at thegeneral purpose processor 308 i. The scheduler circuit 308 b/n canexploit this functionality of the execution resource to queue sessionflows for scheduling downstream. The scheduler circuit 308 b/n can beinformed of the state of the execution resource(s) (e.g., 308 i), thecurrent session that is run on the execution resource; the memory spaceallocated to it, the location of the session context in the processorcache.

According to embodiments, a scheduler circuit 308 b/n can furtherinclude switching circuits to change execution resources from one stateto another. The scheduler circuit 308 b/n can use such a capability toarbitrate between the queues that are ready to be switched into thedownstream execution resource. Further, the downstream executionresource can be optimized to reduce the penalty and overhead associatedwith context switch between resources. This is further exploited by thescheduler circuit 308 b/n to carry out seamless switching betweenqueues, and consequently their execution as different sessions by theexecution resource.

According to embodiments, a scheduler circuit 308 b/n can scheduledifferent sessions on a downstream processing resource, wherein the twoare operated in coordination to reduce the overhead during contextswitches. An important factor in decreasing the latency of services andengineering computational availability can be hardware context switchingsynchronized with network queuing. In embodiments, when a queue isselected by a traffic manager, a pipeline coordinates swapping in of thecache (e.g., L2 cache) of the corresponding resource (e.g., 308 i) andtransfers the reassembled I/O data into the memory space of theexecuting process. In certain cases, no packets are pending in thequeue, but computation is still pending to service previous packets.Once this process makes a memory reference outside of the data swapped,the scheduler circuit (308 b/n) can enable queued data from an I/Odevice 302 to continue scheduling the thread.

In some embodiments, to provide fair queuing to a process not havingdata, a maximum context size can be assumed as data processed. In thisway, a queue can be provisioned as the greater of computational resourceand network bandwidth resource. As but one very particular example, acomputation resource can be an ARM A9 processor running at 800 MHz,while a network bandwidth can be 3 Gbps of bandwidth. Given the lopsidednature of this ratio, embodiments can utilize computation having manyparallel sessions (such that the hardware's prefetching ofsession-specific data offloads a large portion of the host processorload) and having minimal general purpose processing of data.

Accordingly, in some embodiments, a scheduler circuit 308 b/n can beconceptualized as arbitrating, not between outgoing queues at line ratespeeds, but arbitrating between terminated sessions at very high speeds.The stickiness of sessions across a pipeline of stages, including ageneral purpose OS, can be a scheduler circuit optimizing any or allsuch stages of such a pipeline.

Alternatively, a scheduling scheme can be used as shown in U.S. Pat. No.7,760,715 issued to Dalal on Jul. 20, 2010, incorporated herein byreference. This scheme can be useful when it is desirable to rate limitthe flows for preventing the downstream congestion of another resourcespecific to the over-selected flow, or for enforcing service contractsfor particular flows. Embodiments can include arbitration scheme thatallows for service contracts of downstream resources, such as generalpurpose OS that can be enforced seamlessly.

Referring still to FIG. 3, a hardware scheduler according to embodimentsherein, or equivalents, can provide for the classification of incomingpacket data into session flows based on session metadata. It can furtherprovide for traffic management of these flows before they are arbitratedand queued as distinct processing entities on the offload processors.

In some embodiments, offload processors (e.g., 308 i) can be generalpurpose processing units capable of handling packets of differentapplication or transport sessions. Such offload processors can be lowpower processors capable of executing general purpose instructions. Theoffload processors could be any suitable processor, including but notlimited to: ARM, ARC, Tensilica, MIPS, StrongARM or any other processorthat serves the functions described herein. Such offload processors havea general purpose OS running on them, wherein the general purpose OS isoptimized to reduce the penalty associated with context switchingbetween different threads or group of threads.

In contrast, context switches on host processors can be computationallyintensive processes that require the register save area, process contextin the cache and TLB entries to be restored if they are invalidated oroverwritten. Instruction Cache misses in host processing systems canlead to pipeline stalls and data cache misses lead to operation stalland such cache misses reduce processor efficiency and increase processoroverhead.

In contrast, an OS 308 j running on the offload processors 308 i inassociation with a scheduler circuit 308 b/n, can operate together toreduce the context switch overhead incurred between different processingentities running on it. Embodiments can include a cooperative mechanismbetween a scheduler circuit and the OS on the offload processor 308 i,wherein the OS sets up session context to be physically contiguous(physically colored allocator for session heap and stack) in the cache;then communicates the session color, size, and starting physical addressto the scheduler circuit upon session initialization. During an actualcontext switch, a scheduler circuit can identify the session context inthe cache by using these parameters and initiate a bulk transfer ofthese contents to an external low latency memory (e.g., 308 g). Inaddition, the scheduler circuit can manage the prefetch of the oldsession if its context was saved to a local memory 308 g. In particularembodiments, a local memory 308 g can be low latency memory, such as areduced latency dynamic random access memory (RLDRAM), as but one veryparticular embodiment. Thus, in embodiments, session context can beidentified distinctly in the cache.

In some embodiments, context size can be limited to ensure fastswitching speeds. In addition or alternatively, embodiments can includea bulk transfer mechanism to transfer out session context to a localmemory 308 g. The cache contents stored therein can then be retrievedand prefetched during context switch back to a previous session.Different context session data can be tagged and/or identified withinthe local memory 308 g for fast retrieval. As noted above, contextstored by one offload processor may be recalled by a different offloadprocessor.

In the very particular embodiment of FIG. 3, multiple offload processingcores can be integrated into a computation FPGA 308. Multiplecomputational FPGAs can be arbitrated by arbitrator circuits in anotherFPGA 310. The combination of computational FPGAs (e.g., 308) and arbiterFPGAs (e.g., 310) are referred to as “XIMM” modules or “Xockets DIMMmodules” (e.g., computation unit 300). In particular applications, theseXIMM modules can provide integrated traffic and thread managementcircuits that broker execution of multiple sessions on the offloadprocessors.

FIG. 3 also shows an offload processor tunnel connection 308 k, as wellas a memory interface 308 m and port 3081 (which can be an acceleratorcoherency port (ACP)). Memory interface 308 m can access buffer memory308 a.

Having described various embodiments suitable for IO virtualizationoperations, examples illustrating particular aspects of such embodimentswill now be described.

FIG. 4 illustrates an example embodiment of a process 400 that can beexecuted by embodiments to lock the TLB entries. A process may start(402) with a determination being made to forward a packet to an offloadprocessor (404). A memory access request can be generated (406). If thetranslation information is not present in a TLB (IOTLB in the embodimentshown) (No from 408), the transition information can be obtained and theTLB can be updated (410). In some embodiments, such an action caninclude a page table walk. If the translation information is present ina TLB (Yes from 408), a determination is made if the entry in the IOTLBof the translation information is to be locked (412). If the entry isnot to be locked (No from 412), the process can terminate (416). If theentry is to be locked (Yes from 412), the corresponding TLB entry (orentries) can be locked (414), and the process can terminate (416).

FIG. 5 is a block diagram of a virtual switch 106 a′ based on a networkinterface card that can be included in the embodiments (e.g., 106 a ofFIG. 1-0). A virtual switch 106 a′ can receive (514) or transmit (512)packets or other I/O data to or from an external source. Transmitted orreceived data can be processed by a Layer 2 (L2) sorter 510, and heldtemporarily in queues (one shown as 506). In the particular embodimentof FIG. 5, virtual switch 106 a′ can include physical controllingfunctions (CFs) (502 a) or virtual functions (VFs) (502) generated bythe network interface card to receive a packet or other I/O data fromthe network or another computer or virtual machine. In addition, virtualswitch 106 a′ can write a descriptor (one shown as 504) includingdetails of the necessary memory operation for the packet (i.e.read/write, source/destination). Such a descriptor can be assigned avirtual memory location (e.g., by an operating system). Virtual functionreads or writes data between I/O device and system memory locations canthen be executed with a direct memory transfer (e.g., DMA) via a DMAcontroller 518. In this particular embodiment, the network interfacecard can be connected to a host bus 500, which can be a PCI type bus.

It should be appreciated that in the foregoing description of exemplaryembodiments of the invention, various features of the invention aresometimes grouped together in a single embodiment, figure, ordescription thereof for the purpose of streamlining the disclosureaiding in the understanding of one or more of the various inventiveaspects. This method of disclosure, however, is not to be interpreted asreflecting an intention that the claimed invention requires morefeatures than are expressly recited in each claim. Rather, as thefollowing claims reflect, inventive aspects lie in less than allfeatures of a single foregoing disclosed embodiment. Thus, the claimsfollowing the detailed description are hereby expressly incorporatedinto this detailed description, with each claim standing on its own as aseparate embodiment of this invention.

It is also understood that the embodiments of the invention may bepracticed in the absence of an element and/or step not specificallydisclosed. That is, an inventive feature of the invention may beelimination of an element.

Accordingly, while the various aspects of the particular embodiments setforth herein have been described in detail, the present invention couldbe subject to various changes, substitutions, and alterations withoutdeparting from the spirit and scope of the invention.

What is claimed is:
 1. An input-output (IO) virtualization systemconnectable to a network, the system comprising: a second virtual switchconnected to a memory bus and configured to receive network packets froma first virtual switch, and an offload processor module supporting thesecond virtual switch, the offload processor module further comprisingat least one offload processor configured to modify network packets anddirect the modified network packets to the first virtual switch throughthe memory bus.
 2. The system of claim 1 wherein the second virtualswitch receives network packets via memory write operations on thememory bus and sends network packets via the memory read operations onthe memory bus.
 3. The system of claim 1, wherein: the offload processormodule comprises separately addressable offload processors, at least twoof the offload processors being configured to process network packetsdirected to memory addresses corresponding to the offload processors. 4.The system of claim 1 wherein the memory bus supports a dual data rate(DDR) protocol.
 5. The system of claim 4 wherein the protocol is DDR3.6. The system of claim 1 wherein the first virtual switch is configuredto communicate with the second virtual switch by direct memory accesses.7. The system of claim 1 wherein the first virtual switch comprises adirect memory access (DMA) master.
 8. The system of claim 1 wherein thesecond virtual switch comprises a direct memory access (DMA) slave. 9.The system of claim 1 wherein the second virtual switch comprises ascheduler and an arbiter to prioritize handling of network packets. 10.An input-output (IO) virtualization system, comprising: a physical IOdevice, multiple virtual IO devices, and a provisioning agent configuredto allocate address spaces in a main memory to each of the multiplevirtual IO devices and the physical IO device, with each of the physicalor virtual IO devices configured to execute direct memory reads andwrites to their respective address spaces.
 11. The system of claim 10wherein the address spaces can be physical or virtual, and theprovisioning agent is configured to create a mapping between virtualaddresses and physical addresses.
 12. The system of claim 10 furthercomprising multiple offload processors corresponding to a definedaddress space, and wherein the defined address spaces can be physical orvirtual, and the provisioning agent can create a mapping between virtualaddresses and physical addresses.
 13. The system of claim 10, whereinthe provisioning agent is configured to allocate physical addresses forvirtual function (VF) drivers.
 14. The system of claim 10, furtherincluding virtual function (VF) drivers configured to write at least aportion of a descriptor for network packet data processing.
 15. Thesystem of claim 10, further including: the address spaces can bephysical or virtual, and the provisioning agent is configured to createa mapping between virtual addresses and physical addresses, and an inputoutput memory management unit (IOMMU) having tables configured to storethe mapping.
 16. The system of claim 10 further including a plurality ofvirtual function (VF) drivers configured to support direct memoryaccesses to the second virtual switch.
 17. The system of claim 9 whereinthe provisioning agent is executed by at least one host processor.